90 nm generation Cu/CVD low-k (k < 2.5) interconnect technology

Author

Bao, T.I. ; Ko, C.C. ; Song, J.Y. ; Li, L.P. ; Lu, H.H. ; Lu, Y.C. ; Chen, Y.H. ; Jang, S.M. ; Liang, AndM S.

Author_Institution

Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

583

Lastpage

586

Abstract

Eight level Cu/CVD low-k (k<2.5) + one top level Cu/USG 90 nm multilevel interconnection with 0.12/0.12 /spl mu/m for line width/space and 0.13 /spl mu/m for via has been demonstrated for the first time using 193 nm lithography with OPC developed for TSMC 200 mm/300 mm technologies. The 8-level Cu/CVD low-k dual damascenes were constructed by nitrogen-free dielectric layers without middle trench etch stop to achieve keff=2.6. No film delamination was found by film and CMP optimization. Electrical results showed that excellent and thermally stable metal-line Rs and via-chain Rc yields from iso or dense Cu areas and 1M via chains were obtained.

Keywords

ULSI; copper; dielectric thin films; integrated circuit interconnections; thermal stability; ultraviolet lithography; 0.12 micron; 0.13 micron; 193 nm; 200 mm; 300 mm; 90 nm; Cu; Cu/CVD low-k dual damascenes; OPC; ULSI; UV lithography; line width/space; multilevel interconnection; thermally stable metal-line; via chains; Capacitance; Dielectrics; Etching; Integrated circuit interconnections; Lithography; Moisture; Pollution measurement; Space technology; Tensile stress; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175908

Filename

1175908