Title :
A VLSI chip set for a small mainframe processor
Author :
Yamada, S. ; Sano, T. ; Saito, M. ; Motohashi, M. ; Oki, H. ; Tsuruya, H.
Author_Institution :
NEC Corp. Kawasaki, Japan
Abstract :
A CMOS VLSI chip set, which consists of three chips including a chip with 495000 transistors, 0.8-ns gate delay, and a 12-ns RAM, has been developed to achieve a high-performance 32-bit mainframe processor. This chip set uses a 1.2-μm double-diffused-drain transistor, double-layer metallization technology and a sophisticated CAD (computer-aided design) system. Each chip is mounted on a 288-pin surface-mount pin grid array package. A one-board CPU can be realized by assembling the chip set on a multilayer printed wiring board with RAMS and interface LSIs
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; integrated memory circuits; microcomputers; microprocessor chips; random-access storage; 0.8 ns; 1.2 micron; 12 ns; 32 bits; 32-bit mainframe processor; CMOS; MLB; RAM; VLSI chip set; double-diffused-drain transistor; double-layer metallization; interface LSIs; multilayer printed wiring board; one-board CPU; pinout 288 pins; small mainframe processor; surface-mount pin grid array package; three chip set; Assembly; CMOS process; CMOS technology; Delay; Design automation; Electronics packaging; Metallization; Nonhomogeneous media; Read-write memory; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20929
