A 90 nm generation copper dual damascene technology with ALD TaN barrier

As the device dimension continues to shrink, the need for a thinner barrier for copper has risen in order to meet the requirements for future device performance. The conventional barrier process by physical vapor deposition (PVD) has the limitation to achieve conformal step coverage across the dual damascene structure , and therefore would face a bottleneck when the thickness reduction is required. In this work, the atomic layer deposition (ALD) technique is applied for the TaN barrier process of a 90 nm generation copper dual damascene integration with low-k dielectrics of k=3.0. The ALD technique could not only provide a conformal step coverage on both trenches and vias, it could also allows reasonable thickness control for thickness of the order of 10 /spl Aring/. The integration results show that ALD TaN has promising electrical performance on sheet resistance, via resistance, and line-to-line leakage, and it also has superior reliability performance on electromigration, stress migration, and bias temperature test as compared with conventional PVD TaN.