Intrinsic evolution of digital-to-analog converters using a CMOS FPTA chip

The work presented here tackles the problem of designing a unipolar 6-bit digital-to-analog converter (DAC) with a voltage mode output by hardware evolution. Thereby a field programmable transistor array (FPTA) is used as the analog substrate for testing the candidate solutions. The FPTA features 256 programmable transistors, whose channel geometry and routing can be configured to form a large variety of transistor level analog circuits. A series of experiments reveals that variations of the output voltage range influence evolution´s success more severely than varying the amount of available electronic resources or the geometrical setup. Although a considerable number of runs yield converters with a nonlinearity of less than 1 bit, no DAC is found to maintain a nonlinearity of less than 0.5 bits under worst case conditions, as required for a true 6-bit resolution. While the evolved circuits work comparably well at different time scales as well as on different dice, they lack the ability to abstract from the analog voltage levels of the digital input signals. It is experimentally verified that this can be remedied by inserting digital buffers at the circuits´ inputs.