Title :
14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide
Author :
Hokazono, A. ; Ohuchi, K. ; Takayanagi, M. ; Watanabe, Y. ; Magoshi, S. ; Kato, Y. ; Shimizu, T. ; Mori, S. ; Oguma, H. ; Sasaki, T. ; Yoshimura, H. ; Miyano, K. ; Yasutake, N. ; Suto, H. ; Adachi, K. ; Fukui, H. ; Watanabe, T. ; Tamaoki, N. ; Toyoshima,
Author_Institution :
SoC Res. & Dev. Center, Toshiba Corp. Semicond. Co., Yokohama, Japan
Abstract :
High performance 14 nm gate length CMOSFETs are demonstrated in this paper. To acquire a shallow source/drain (S/D) extension profile, the optimization of a low thermal budget process utilizing poly-SiGe and Ni salicide is performed. A poly-SiGe gate electrode minimizes the gate depletion effect, so that a high level of dopant activation in the gate electrode is realized even by low temperature spike annealing. Moreover, short channel characteristics are optimized by using an offset spacer beside the gate electrode. The highest drive current is achieved in 14 nm gate length CMOSFETs reported to date.
Keywords :
Ge-Si alloys; MOSFET; annealing; ion implantation; nanotechnology; nitridation; semiconductor device measurement; semiconductor device metallisation; 14 nm; 14 nm gate length CMOSFETs; Ni salicide; NiSi; SiGe; dopant activation level; drive current; gate depletion effect minimization; implantation condition; low temperature spike annealing; low thermal budget process; offset spacer; oxynitridation process; poly-SiGe gate electrode; shallow source/drain extension profile; short channel characteristics; source/drain engineering; Annealing; CMOSFETs; Cobalt; Dielectric losses; Electrodes; Leakage current; Manufacturing processes; Plasma devices; Plasma temperature; Toy manufacturing industry;
Conference_Titel :
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7462-2
DOI :
10.1109/IEDM.2002.1175920
