Power-constrained device and technology design for the end of scaling

Author

Frank, David J.

Author_Institution

Semicond. Res. & Dev. Center (SRDC), IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

643

Lastpage

646

Abstract

This paper argues that the end of scaling is full technology optimization, and shows how application-dependent power dissipation constraints can be incorporated into system-level analyses to yield optimal device and technology design parameters. A new optimization criteria, ROI (Return on Investment), is introduced, and dependencies on underlying assumptions are investigated.

Keywords

circuit optimisation; integrated circuit design; integrated circuit economics; integrated circuit technology; investment; ROI optimization criteria; optimal device design parameters; optimal technology design parameters; power-constrained device design; power-constrained technology design; return on investment; scaling; system-level analyses; technology optimization; CMOS technology; Constraint optimization; Costs; Design optimization; Power dissipation; Power generation economics; Research and development; Threshold voltage; Tunneling; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175921

Filename

1175921

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3130483