Title :
0.1 /spl mu/m RFCMOS on high resistivity substrates for system on chip (SOC) applications
Author :
Yang, J.-Y. ; Benaissa, K. ; Crenshaw, D. ; Williams, B. ; Sridhar, S. ; Ai, J. ; Boselli, G. ; Zhao, S. ; Tang, S.-P. ; Mahalingam, N. ; Ashburn, S. ; Madhani, P. ; Blythe, T. ; Shichijo, H.
Author_Institution :
Texas Instrum., Dallas, TX, USA
Abstract :
This paper describes the impact of substrate resistivity on the key components of the radio frequency (RF) CMOS for the system on chip (SOC) applications. The comparison includes the transistor, inductor, capacitor, noise isolation, latch-up as well as the well-to-well isolation in a 0.1 /spl mu/m (physical gate length) CMOS technology.
Keywords :
CMOS integrated circuits; integrated circuit noise; integrated circuit reliability; mixed analogue-digital integrated circuits; radiofrequency integrated circuits; system-on-chip; 0.1 micron; RF/digital/analog functions; RFCMOS; SOC; capacitor; high resistivity substrates; inductor; latch-up; noise isolation; reliability; substrate resistivity; system on chip applications; well-to-well isolation; CMOS process; CMOS technology; Capacitors; Conductivity; Degradation; Impedance; Inductors; Isolation technology; Radio frequency; System-on-a-chip;
Conference_Titel :
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7462-2
DOI :
10.1109/IEDM.2002.1175927
