An advanced triple level metal CMOS technology for ASIC applications

Author

Schmiesing, John ; Chang, K.Y. ; Pintchovski, Fabio ; Klein, Jeff ; Baker, Kelly ; Meyer, Charles S. ; Lai, Steve ; Hoang, David ; Tang, Dandas

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

1988

fDate

16-19 May 1988

Abstract

An advanced triple-level metal CMOS technology (TRIM), which uses a twin-well approach to achieve optimal device performance, is described in detail with emphasis on novel process like borophosphosilicate glass wet/dry etch, barrier metal, and boron-doped silica glass. Degradation of device reliability due to the triple-level metal (TLM) is also discussed. A 100 K gate array has been successfully manufactured utilizing this technology. NAND gate delays of 250 ps at V_dd of 5 V have been demonstrated. The Motorola automatic routing tool can achieve a very high gate utilization efficiency of 80% as a result of the use of the third-level metal

Keywords

CMOS integrated circuits; VLSI; cellular arrays; integrated circuit technology; integrated logic circuits; metallisation; 100 K gate array; 250 ps; 5 V; 80 percent; ASIC applications; B2O3-P2O5-SiO2; BPSG; CMOS technology; Motorola automatic routing tool; NAND gate delays; SiO₂:B glass; TLM; TRIM; barrier metal; borophosphosilicate glass wet/dry etch; gate utilization efficiency; glass; optimal device performance; reliability; third-level metal; triple level metal; twin-well approach; Application specific integrated circuits; CMOS process; CMOS technology; Degradation; Delay; Dry etching; Glass; Manufacturing; Silicon compounds; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/CICC.1988.20932

Filename

20932