An efficient fault-tolerant VLSI architecture using parallel evolvable hardware technology

This paper proposes a novel, fault-tolerant, VLSI architecture, which utilizes an evolvable hardware (EHW) framework using a parallel evolutionary algorithm (EA). The architecture consists of two layers. The first layer considers the application in hand, whereas the second is used as a controller that monitors the performance of the first layer and reconfigures when appropriate, its computational elements. The demonstration of this architecture is done through a practical example of a Global Positioning System (GPS) attitude determination system. Firstly the structure and functionality of both layers is described. Subsequently, the paper provides results that demonstrate both the reliability and performance of the system, while various quantities of faults are simultaneously injected in both layers. According to these results, the first layer is capable to cope with higher amount of faults (worst-case scenario 35-40%) than the second (control) layer, which copes with faults that capture in worst-case scenario the 30% of its resources. Finally, an additional mechanism to this architecture is proposed that needs further investigation and promises further enhancing of the systems reliability.