A genetic algorithm for the optimisation of a reconfigurable pipelined FFT processor

Author

Sulaiman, Nasri ; Arslan, Tughrul

Author_Institution

Dept. of Electron. & Electr. Eng., Edinburgh Univ., UK

fYear

2004

fDate

24-26 June 2004

Firstpage

104

Lastpage

108

Abstract

This paper describes the optimisation of the word length in a 16-point radix-4 reconfigurable pipelined fast Fourier transform (FFT) based receiver device. Two forms of optimisation; input data optimisation and FFT coefficients optimisation are investigated in this paper. The word length for input data and FFT coefficients are initially set to 16-bits. A genetic algorithm (GA) is then used to find the optimal word length for the input data and FFT coefficients while satisfying functionality constraints. The GA is able to determine an optimised word length down to 10 bits for input data and 8 bits for the FFT coefficients.

Keywords

circuit optimisation; fast Fourier transforms; genetic algorithms; microprocessor chips; pipeline arithmetic; reconfigurable architectures; 16 bits; 16-point radix-4 processor; FFT coefficients optimisation; fast Fourier transform; genetic algorithm; input data optimisation; pipelined FFT processor; receiver device; reconfigurable processor; word length optimisation; Digital signal processing; Discrete Fourier transforms; Fast Fourier transforms; Finite impulse response filter; Genetic algorithms; Hardware; IIR filters; OFDM; Signal processing algorithms; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Evolvable Hardware, 2004. Proceedings. 2004 NASA/DoD Conference on

Print_ISBN

0-7695-2145-2

Type

conf

DOI

10.1109/EH.2004.1310817

Filename

1310817