Metaprogramming in digital simulation

This paper describes the use of metaprogramming in Prolog to construct digital logic-simulators which adapt themselves for efficiency to the structure of the circuits they simulate. To test the utility of the metaprogramming approach to simulation, in a simple but representative domain, a logic-simulator was written for TTL integrated circuits. The simulator accepts a wiring-list, from which it creates, loads, and executes a Prolog rule which is both (a) a representation of the user´s circuit at the level of gates, adders, counters, etc., and (b) a procedure for its simulation. This rule, which expresses the structure of the circuit by means of Clocksin´s definitional format, is an example of “executable data”; there is no distinction in Prolog, that is, between executable code and data. The ordering of goals in this rule guarantees that signals are traced through the circuit with no backtracking; thus the time to execute a simulation-cycle is minimized