True influence of wafer-backside copper contamination during the back-end process on device characteristics

Author

Hozawa, K. ; Miyazaki, H. ; Yugami, J.

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

737

Lastpage

740

Abstract

The influence of backside Cu contamination during the back-end process on the electrical characteristics of MOSFETs was revealed. The influence is well explained in terms of Cu diffusion behavior at 400/spl deg/C, which strongly depends on SiO/sub 2/ thickness at front and back sides of wafers. Cu atoms brought into the Si wafer can not diffuse into the thick front-side SiO/sub 2/ film, but Cu atoms exist inside Si near the SiO/sub 2//Si interface after annealing. Accordingly, backside Cu contamination during the back-end process does not affect Time Zero Dielectric Breakdown (TZDB), Dit, or Vfb, but it decreases Time Dependent Dielectric Breakdown (TDDB) lifetime and drastically enhances short-channel effect due to impurity compensation.

Keywords

MOS capacitors; MOSFET; annealing; diffusion; semiconductor device breakdown; semiconductor device metallisation; solid solubility; surface contamination; 10 min; 400 C; 60 min; Cu diffusion behavior; MOS capacitors; MOSFETs; SiO/sub 2/ thickness; SiO/sub 2/-Si:Cu; SiO/sub 2//Si interface; TDDB lifetime; annealing; back-end process; electrical characteristics; impurity compensation; short-channel effect; time dependent dielectric breakdown; time zero dielectric breakdown; wafer-backside Cu contamination; wiring material; Annealing; Copper; Dielectric breakdown; Electric variables; MOS capacitors; MOSFETs; Optical films; Pollution measurement; Surface contamination; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175943

Filename

1175943