Title :
A self-timed structural test methodology for timing anomalies due to defects and process variations
Author_Institution :
Electr. & Comput. Eng., Auburn Univ., AL
Abstract :
We present a new structural self-timed delay test methodology that identifies timing anomalies in the circuit by comparing the relative switching time of the different signal lines feeding the scan chains. These are observed by capturing the circuit´s response to a delay test at multiple sample times, at and below the design cycle time. A timing defect is detected if there is a reversal in the switching order of any two outputs from that reliably predicted by simulation (or measurement on golden circuits), while allowing for processes variations
Keywords :
automatic test pattern generation; boundary scan testing; delays; fault diagnosis; integrated circuit testing; logic circuits; logic testing; circuit testing; delay test; delay testing; processes variations; relative switching time; scan chains; self-timed structural test methodology; switching order; timing anomalies; Automatic testing; CMOS logic circuits; Circuit faults; Circuit testing; Clocks; Delay effects; Fault detection; Propagation delay; Switching circuits; Timing;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1583964
