Testing and debugging delay faults in dynamic circuits

We propose novel design for test and debug techniques to apply two patterns for delay fault test and debug in dynamic circuits. Dynamic circuits, which have traditionally been difficult to test, pose new challenges for AC tests due to the presence of a reset phase between applications of any two patterns, which impedes delay fault testing of such circuits. We present two sets of design for test and debug techniques. The first set facilitates application of two patterns to dynamic circuits in general, overcoming the issue of reset phase, and reduces the problem of test generation for dynamic circuits to test generation for pull down paths of static CMOS circuits. The second set enables application of two patterns to scan based dynamic circuits. The proposed techniques reduce the problem of delay test generation for scan based dynamic circuits to that of delay test generation for static CMOS circuits with complete accessibility to all primary inputs. The techniques have minimal area overhead and also provide significant reduction in power during scan operation