Testability features of the first-generation CELL processor

Author

Riley, Mack ; Bushard, Louis ; Chelstrom, Nathan ; Kiryu, Naoki ; Ferguson, Steven

Author_Institution

IBM Syst. & Technol., Austin, TX

fYear

2005

fDate

8-8 Nov. 2005

Lastpage

119

Abstract

The first generation CELL processor presented a test challenge in that the chip incorporated multiple processing elements, several multi-gigahertz synchronous and asynchronous clock domains, and many custom design elements. The test objective for the CELL design was to have high test coverage and a small test time. In addition to the objectives mentioned above, the CELL test logic is designed to support a modular design point and support for partial good processing elements. This paper will give an overview of the manufacturing test elements that were designed into the CELL processor

Keywords

automatic test pattern generation; boundary scan testing; built-in self test; clocks; logic testing; microprocessor chips; CELL design; custom design elements; first generation CELL processor; modular design point; multigigahertz asynchronous clock domains; multiple processing elements; test coverage; test elements manufacturing; test logic; test time; Clocks; Communication system control; Logic devices; Logic testing; Microwave integrated circuits; Multicore processing; Process design; Random access memory; Semiconductor device testing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2005. Proceedings. ITC 2005. IEEE International

Conference_Location

Austin, TX

Print_ISBN

0-7803-9038-5

Type

conf

DOI

10.1109/TEST.2005.1583967

Filename

1583967