Title :
Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis
Author :
Schuermyer, C. ; Cota, K. ; Madge, R. ; Benware, B.
Author_Institution :
LSI Logic Corp.
Abstract :
Traditional yield analysis has been focused on wafer fabrication and process improvement and is generally limited to wafer level visualization. As products get more complex and design practices have more impact on yield, visualization of yield issues inside the chip becomes increasingly critical. This paper presents novel visualization and analysis of volume structural test fail data to aid in the identification of yield weaknesses through relative analysis of fail signatures. The results show that these methodologies can identify subtle process/design yield limiters which cannot be identified using traditional yield analysis methodologies
Keywords :
application specific integrated circuits; boundary scan testing; data visualisation; failure analysis; flip-flops; integrated circuit testing; integrated circuit yield; logic testing; complex ASICS; data analysis; data visualization; fail signatures; process improvement; systematic yield limiters; volume structural test fail data; wafer fabrication; wafer level visualization; yield analysis methodologies; Application specific integrated circuits; Data analysis; Data visualization; Fabrication; Failure analysis; Inspection; Large scale integration; Logic testing; Process design; System testing;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1583970