Recoded versus nonrecoded signed-digit number based digital parallel arithmetic: a case study

Digital implementations for both the recoding and the addition steps for the signed-digit numbers require four or more logic levels (AND-OR) or (OR-AND) and at least 23 logic gates for each output bit. In this paper, a much simpler nonrecoding signed-digit adder is presented. Its hardware implementation requires much fewer logic gates and inputs lines than that for the recoded signed-digit one for the same number of logic levels