The evaluation of assembly process for package on package components

The Package on Package (PoP) component is getting attentions in mobile communication electronics industry to meet the miniaturization requirements. The 3D IC packaging technology is employed to achieve higher integrations for multiple functions. This also concurrently reduces the size of PCB during second level of interconnection. Currently, there are two major approaches for system manufactures. The first approach is to purchase the stacked PoP from component supplier. The alternative is to assemble the non-stacked PoP components in house. This study investigates the influences of soldering materials during top chip assembly. Two types of solder pastes and one paste flux are evaluated. The amount of dipping is also characterized. Dipping depths of 37% and 50% of the ball heights are considered. The bottom chips (test vehicle) are daisy chained with single electrical loop. The top chips have center loop and peripheral loop. The PoP components are placed onto center location and area near the edge to study the influence if any.