Title :
A novel process and hardware architecture to reduce burn-in cost
Author :
Schroeder, Chris ; Pan, Jin ; Albertson, Todd
Abstract :
This paper presents a novel process and hardware architecture that dramatically reduces the cost of burn-in for performance CPUs. This also demonstrates that Moore´s law can be sustained for BI in face of many challenges
Keywords :
integrated circuit testing; microprocessor chips; Moore law; burn-in cost reduction; hardware architecture; process architecture; Acceleration; Bismuth; Cogeneration; Costs; Hardware; Manufacturing; Temperature distribution; Testing; Thermal stresses; Voltage;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1584002
