• DocumentCode
    3131628
  • Title

    Experimental investigation and finite element analysis of bump wafer probing

  • Author

    Chang, Hao-Yuan ; Pan, Wen-Fung ; Shih, Meng-Kai ; Lai, Yi-Shao

  • Author_Institution
    Adv. Semicond. Eng., Inc., Kaohsiung, Taiwan
  • fYear
    2009
  • fDate
    21-23 Oct. 2009
  • Firstpage
    514
  • Lastpage
    517
  • Abstract
    The purpose of this paper is to analyze the bump height variation and probe mark profile with various bump materials for wafer probing. It is necessary to establish different material bump wafer probing criteria, because the bump height variation and probe mark area have severe influence on the sort flip chip wafers that will affects the quality of the contact behavior and further impacts the flip chip assembly process reliability after wafer level probing. Standard bump wafer probing parameters can not only satisfy customer´s various characters of devices, but is easy to control the appropriate bump height and probe mark quality to ensure assembly process reliability and to avoid the cold joint issue. In this paper, probing bump height and probe mark configuration with different bump materials were performed and the resultant probe marks from experiment were verified against the FE simulation results. A three-dimensional computational model was developed for analyze the contact phenomena of the solder bump and the probe. Finally, the standard bump wafer probing criteria were built by the experimental results and numerical methods. They can be used as the verified simulating model which is a useful performance evaluation tool to support the choice of suitable probe recipes and wafer probe parameters with more different bump dimensions and materials of wafer probing.
  • Keywords
    finite element analysis; flip-chip devices; integrated circuit reliability; integrated circuit testing; microassembling; probes; wafer level packaging; bump height variation; bump materials; bump wafer probing; finite element analysis; flip chip assembly process reliability; flip chip wafers; probe mark profile; solder bump; three-dimensional computational model; wafer level testing; Artificial intelligence; Assembly; Computational modeling; Finite element methods; Flip chip; Geometry; Probes; Semiconductor device modeling; Semiconductor materials; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009. IMPACT 2009. 4th International
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-4341-3
  • Electronic_ISBN
    978-1-4244-4342-0
  • Type

    conf

  • DOI
    10.1109/IMPACT.2009.5382232
  • Filename
    5382232