• DocumentCode
    3132185
  • Title

    Built-in constraint resolution

  • Author

    Giles, Grady ; Irby, Joel ; Toneva, Daniela ; Tsai, Kun-Han

  • fYear
    2005
  • fDate
    8-8 Nov. 2005
  • Lastpage
    706
  • Abstract
    A scan circuit construction obviates ATPG constraints for the prevention of tristate contention on internal tristate busses and one-hot muxes. The circuit is supported by enhanced ATPG
  • Keywords
    automatic test pattern generation; built-in self test; logic testing; ATPG constraints; built-in constraint resolution; one-hot muxes; scan circuit; tristate busses; tristate contention; Automatic test pattern generation; Circuit testing; Clocks; Decoding; Driver circuits; Microprocessors; Sequential analysis; System testing; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2005. Proceedings. ITC 2005. IEEE International
  • Conference_Location
    Austin, TX
  • Print_ISBN
    0-7803-9038-5
  • Type

    conf

  • DOI
    10.1109/TEST.2005.1584032
  • Filename
    1584032
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3132185