Title :
Resistorless ESD protection device for high speed CMOS circuits
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
Abstract :
A novel, resistorless electrostatic-discharge (ESD)-protection device for high-speed CMOS circuits, consisting of two thick oxide n-channel MOSFETs in the same p-well, has been designed, fabricated, and tested. It can be used to protect inputs or outputs. The advantages include (1) minimum input RC delay time minimized; (2) no power consumption even if input voltage goes above 5-V power supply; (3) military ESD specification exceeded with small layout size; and (4) no latch-up due to input overvoltage stress
Keywords :
CMOS integrated circuits; electrostatics; insulated gate field effect transistors; ESD protection device; high speed CMOS circuits; inputs; latch-up; layout size; military ESD specification; minimum input RC delay time; outputs; p-well; power consumption; resistorless; thick oxide n-channel MOSFETs; Breakdown voltage; Circuit testing; Delay effects; Electrostatic discharge; MOSFETs; Power supplies; Protection; Resistors; Semiconductor diodes; Variable structure systems;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20943
