Title :
Hierarchical DFT with enhancements for AC scan, test scheduling and on-chip compression - a case study
Author :
Remmers, Jeffrey ; Lee, Darin ; Fisette, Richard
Author_Institution :
Plexus Design Solutions, Inc., Sudbury, MA
Abstract :
The DFT architecture, pattern generation and application, and economic issues encountered in large ASIC designs are increased when at-speed testing is introduced. This case study shows enhancements over the current state of the art hierarchical methodology by improving transition testing, test scheduling, and using compression on a production design
Keywords :
design for testability; integrated circuit design; production testing; scheduling; system-on-chip; AC scan; at-speed testing; economic issues; hierarchical DFT; large ASIC designs; on-chip compression; pattern generation; production design; test scheduling; transition testing; AC generators; Application specific integrated circuits; Computer aided software engineering; Design for testability; Logic devices; Logic testing; Production systems; System testing; System-on-a-chip; Test pattern generators;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1584034
