Thermal and electrical transients during ESD stress

A novel approach is presented for predicting the harmful temperatures and voltage present during electrostatic-discharge (ESD) stress. The analytical model based on a thermal equivalent circuit, predicts a maximum temperature as a function of process and design variables. Damaging electrical voltages are predicted in a similar manner. A viable ESD design methodology evolves out of the above models, and an outline of such a methodology is discussed. Further work needed towards the design of practical ESD protection circuits is examined