DocumentCode
3132301
Title
Gate exhaustive testing
Author
Cho, Kyoung Youn ; Mitra, Subhasish ; McCluskey, Edward J.
Author_Institution
Departments of Electr. Eng. & Comput. Sci., Stanford Univ., CA
fYear
2005
fDate
8-8 Nov. 2005
Lastpage
777
Abstract
A gate exhaustive test set applies all possible input combinations to each gate in a combinational circuit, and observes the gate response at an observation point such as a primary output or a scan cell. In this paper, we analyze the effectiveness of the gate exhaustive test metric in detecting defective chips, and compare it with the single stuck-at fault, the N-detect, and the transition fault test metrics. Results from the Stanford CRC ELF35 and ELF18 test experiments show that gate exhaustive test sets are more efficient than single stuck-at and N-detect test sets in terms of the ability to detect defective chips and test length. It is also shown that test sets with higher values of the gate exhaustive coverage have better test quality
Keywords
combinational circuits; fault diagnosis; logic gates; logic testing; N-detect test; combinational circuit; gate exhaustive testing; gate response; stuck-at faults; test quality; transition fault test; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Combinational circuits; Cyclic redundancy check; Electrical fault detection; Fault detection; Semiconductor device measurement; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location
Austin, TX
Print_ISBN
0-7803-9038-5
Type
conf
DOI
10.1109/TEST.2005.1584040
Filename
1584040
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