Word line pulsing technique for stability fault detection in SRAM cells

Author

Pavlov, Andrei ; Azimane, Mohamed ; De Gyvez, Jose Pineda ; Sachdev, Manoj

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont.

fYear

2005

fDate

8-8 Nov. 2005

Lastpage

825

Abstract

Stability testing of SRAMs has been time consuming. This paper presents a new programmable DFT technique for detection of stability and data retention faults in SRAM cells. The proposed technique offers extended flexibility in setting the weak overwrite test stress, which allows to track process changes without time-consuming post-silicon design iterations. Moreover, it does not introduce extra circuitry in the SRAM array and surpasses the data retention test in test time and detection capability

Keywords

SRAM chips; circuit stability; design for testability; fault diagnosis; fault location; integrated circuit reliability; SRAM array; SRAM cells; data retention faults; data retention test; design for testability; overwrite test stress; programmable DFT technique; stability fault detection; stability testing; word line pulsing; Circuit faults; Circuit noise; Circuit stability; Circuit testing; Degradation; Electrical fault detection; Fault detection; Random access memory; Stress; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2005. Proceedings. ITC 2005. IEEE International

Conference_Location

Austin, TX

Print_ISBN

0-7803-9038-5

Type

conf

DOI

10.1109/TEST.2005.1584045

Filename

1584045

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3132389