Design methodology for defect tolerant integrated circuits

A single-spot defect which deforms the power of clock connections of a VLSI IC may affect the functionality of an entire die. Typical yield prediction procedures applied to circuits with redundancy do not take this possibility into account. Analysis of the defect´s nature combined with the appropriate modifications of the existing models is used to address this problem. Applications of the yield models to ICs with redundancy indicate that direct power-ground or clock shorts are a very important limitation to the maximal size of such circuits. A novel design approach that uses circuit breakers to minimize consequences of shorts in the metallization of the IC with redundancy is indicated as a necessity for large-area defect-tolerant circuits