CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system

Author

Suda, Masakatsu ; Yamamoto, Kazuhiro ; Okayasu, Toshiyuki ; Kantake, Shusuke ; Sudou, Satoshi ; Watanabe, Daisuke

Author_Institution

ADVANTEST Corp., Gunma

fYear

2005

fDate

8-8 Nov. 2005

Lastpage

866

Abstract

This paper presents solutions to realize a high-speed, high-precision CMOS timing generator for a 4.266-Gbps memory test system. In order to realize such a timing generator, we developed a 1.066-GHz CMOS timing generator circuit using a high-speed digital delay locked loop circuit and a high-speed, low-INL fine delay circuit. Consequently, we realized a timing generator with 1/20 the size, 4/9 the power, and frac12 the timing error (INL = 8 ps, total jitter =16.8 ps) compared with a conventional timing generator fabricated by the same CMOS process

Keywords

CMOS digital integrated circuits; UHF integrated circuits; digital phase locked loops; high-speed integrated circuits; timing circuits; timing jitter; 1.066 GHz; 16.8 ps; 4.266 Gbit/s; 8 ps; CMOS memory circuit; CMOS timing generator; digital delay locked loop circuit; high-precision timing generator; high-speed timing generator; memory test system; timing jitter; CMOS process; Clocks; Costs; Delay effects; Frequency; Logic circuits; Power generation; Signal generators; System testing; Timing jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2005. Proceedings. ITC 2005. IEEE International

Conference_Location

Austin, TX

Print_ISBN

0-7803-9038-5

Type

conf

DOI

10.1109/TEST.2005.1584050

Filename

1584050