DocumentCode
3132478
Title
A 2.5-Gbps De-Skew Chip for Very Short Reach (VSR) Interconnects
Author
Tang, Wei ; Plant, David V.
Author_Institution
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que.
fYear
2006
fDate
Oct. 2006
Firstpage
823
Lastpage
824
Abstract
We designed and implemented a de-skew chip for parallel optical interconnects. The de-skew ability is limited by the line rate and rising/falling time. We modeled and tested the upper boundary of the maximum allowed channel skew that can be corrected by using this method. This is proved to be a simple and effective way at low line rates at around 2.5 Gbps. For higher line rates, per-pin de-skew scheme is necessary to successfully de-skew all channels with excessive amount of channel skew
Keywords
integrated optoelectronics; optical design techniques; optical interconnections; parallel processing; 2.5 Gbit/s; channel skew; de-skew chip design; parallel optical interconnects; very short reach interconnects; Circuits; Clocks; Delay; Latches; Optical interconnections; Phase locked loops; Sampling methods; Timing; Transceivers; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Lasers and Electro-Optics Society, 2006. LEOS 2006. 19th Annual Meeting of the IEEE
Conference_Location
Montreal, Que.
Print_ISBN
0-7803-9555-7
Electronic_ISBN
0-7803-9555-7
Type
conf
DOI
10.1109/LEOS.2006.279041
Filename
4054439
Link To Document