• DocumentCode
    3132556
  • Title

    Efficient compression of deterministic patterns into multiple PRPG seeds

  • Author

    Wohl, Peter ; Waicukauski, John A. ; Patel, Sanjay ; Dasilva, Francisco ; Williams, T.W. ; Kapur, Rohit

  • Author_Institution
    Synopsys Inc., Mountain View, CA
  • fYear
    2005
  • fDate
    8-8 Nov. 2005
  • Lastpage
    925
  • Abstract
    Recent test-cost reduction methods are based on controlling the initial state (seed) of a pseudo-random pattern generator (PRPG) so that deterministic values are loaded in selected scan cells. Combined with an unload-data compression technique, PRPG seeding reduces test data volume and application time. This paper presents a method of mapping each scan load to multiple PRPG seeds, computed so that test pattern count, data volume, and, therefore, test cost are minimized. This method also allows smaller and fewer PRPGs, reducing the area overhead of test-compression circuitry. The results on deep-submicron industrial designs, show significant test cost reduction when this method is applied with either X-tolerant or X-free unload-data compression
  • Keywords
    automatic test pattern generation; data compression; logic testing; deterministic patterns; multiple PRPG seeding; pseudorandom pattern generator; scan load mapping; test-compression circuitry; test-cost reduction; unload-data compression; Automatic test pattern generation; Built-in self-test; Circuit faults; Circuit testing; Clocks; Codecs; Costs; Delay; Merging; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2005. Proceedings. ITC 2005. IEEE International
  • Conference_Location
    Austin, TX
  • Print_ISBN
    0-7803-9038-5
  • Type

    conf

  • DOI
    10.1109/TEST.2005.1584057
  • Filename
    1584057