DocumentCode
3132568
Title
Floor plan design for 3D multi-layer substrate
Author
Ko, Ching-Mai ; Huang, Yu-Jung ; Fu, Shen-Li
Author_Institution
Dept. of Electron. Eng., I-Shou Univ., Kaohsiung, Taiwan
fYear
2009
fDate
21-23 Oct. 2009
Firstpage
705
Lastpage
708
Abstract
In this paper, a floor plan design application for multilayer substrate is implemented. The simplified evaluation method for thermal, routing and area criterions are discussed and implemented. And then normalize the criterions before the substrate floor plan such that the settings for substrate floor plan are reasonable. And finally, the calculated routing length, area and ANSYS thermal simulation results are compared.
Keywords
integrated circuit layout; network routing; substrates; three-dimensional integrated circuits; 3D multilayer substrate; ANSYS thermal simulation; embedded passive technology; floor plan design; routing length; substrate area; Copper; Design engineering; Design optimization; Gallium nitride; Heat engines; Lasers and Electro-Optics Society; Light emitting diodes; Power generation; Temperature; Thermal resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009. IMPACT 2009. 4th International
Conference_Location
Taipei
Print_ISBN
978-1-4244-4341-3
Electronic_ISBN
978-1-4244-4342-0
Type
conf
DOI
10.1109/IMPACT.2009.5382285
Filename
5382285
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