Design and development of a low cost satellite imaging payload using COTS components with added fault tolerance

This work aims to address the fault tolerance issues in design, implemention and testing of a low-cost imaging payload for a small cube satellite using COTS material. It proposes a test-bed for simulating single-event upset (SEU) phenomenon in memory chips of satellite and evaluating tolerance of onboard JPEG compression algorithm. Single event upset (SEU) causes bit flips in memory circuits without any damage or interference in operation. A method is developed for simulating radiation-induced bit flips using Montë Carlo fault-injection method and quantitatively evaluating the sensitivity of JPEG compression algorithm. Markov chains have been used in simulations of random SEU´s for N hours. It was found that for low-earth orbit missions, no radiation-hardening of memory is needed and occasional memory `scrubbing´ operation will suffice. It was also found that JPEG algorithm has low sensitivity and high tolerance to errors induced by SEU´s.