Device performance improvement with Nitrogen implanted during LDD sequence

Author

Auriac, N. ; Laviron, C. ; Cagnat, N. ; Singer, J. ; Duriez, B. ; Gwoziecki, R. ; Chabanne, G. ; Rando, C.

Author_Institution

Freescale Semicond., Crolles

fYear

2007

fDate

8-9 June 2007

Firstpage

13

Lastpage

16

Abstract

As CMOS gate dimension scale down, control of lateral and vertical diffusion of dopants is required to enhance performance. In this work, device performance with nitrogen implanted in the region between LDD and pocket was investigated. During annealing, N diffuses quickly towards the interface oxide/silicon. The mechanism of N diffusion by interstitial inhibit boron diffusion. By assuming that small amount of B segregates to the interface, simulation have shown that interface states are neutralized by N trapped at the interface oxide/silicon and can improve on state current.

Keywords

CMOS integrated circuits; annealing; boron; elemental semiconductors; impurity distribution; interface states; ion implantation; nitrogen; segregation; semiconductor device models; semiconductor doping; semiconductor-insulator boundaries; silicon; CMOS gate; LDD sequence; Si:N,B; annealing; dopant diffusion; interface states; nitrogen implantation; oxide-silicon interface; pocket; segregation; Annealing; Boron; Conferences; Fabrication; Implants; Leakage current; MOS devices; Microelectronics; Nitrogen; Performance gain;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology, 2007 International Workshop on

Conference_Location

Kyoto

Print_ISBN

1-4244-1103-3

Electronic_ISBN

1-4244-1104-1

Type

conf

DOI

10.1109/IWJT.2007.4279935

Filename

4279935