• DocumentCode
    3132977
  • Title

    20 µm-pitch complaint-bump-bonded chip-on-flex by pre-applied wafer level adhesives

  • Author

    Chuang, Chun-Chih ; Lu, Su-Tsai ; Chang, Tao-Chih ; Suk, Kyoung-Lim ; Paik, Kyung-Wook

  • Author_Institution
    Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
  • fYear
    2009
  • fDate
    21-23 Oct. 2009
  • Firstpage
    56
  • Lastpage
    59
  • Abstract
    A novel process which combined wafer level package technology with ultra-fine pitch chip-on-flex (COF) by sidewall-insulated compliant bumps was developed. We laminated two types of adhesives, single-layer non-conductive adhesive (NCA) and double-layer of non-conductive adhesive/anisotropic conductive adhesive (NCA/ACA), on wafers, respectively. After wafers with laminated adhesives were diced into chips, thermo-compression bonding process was executed by using high accuracy flip-chip bonder. Proper bonding parameters, such as bonding temperature, time, and pressure, were performed during bonding process. Both mechanical and electrical tests were carried out to evaluate bonding quality of adhesive-bonded COFs. 90-degree of peeling test was conducted as mechanical test to evaluate adhesion of bonding interface. Measurements of electrical insulating resistance and 606 I/Os daisy chain resistance were conducted. The reliability of pre-applied adhesive COFs with 20 μm-pitch sidewall-insulated compliant bumps was also examined. Samples that passed electrical tests were then performed to reliability test in terms of thermal humidity storage test (THST) with 85% related humidity (RH) at 85°C. From the results presented, 20 μm-pitch sidewall-insulated compliant-bump-bonded COF packages with pre-applied NCA and NCA/ACA chips were successfully demonstrated. It showed high reliability and potentiality for ultra-fine pitch COF interconnections.
  • Keywords
    adhesive bonding; electronics packaging; lead bonding; anisotropic conductive adhesive; bonding interface; electrical insulating resistance; flip-chip bonder; laminated adhesives; mechanical test; peeling test; pitch complaint-bump-bonded chip-on-flex; preapplied wafer level adhesives; sidewall-insulated compliant bumps; single-layer nonconductive adhesive; thermal humidity storage test; thermocompression bonding process; ultra-fine pitch chip-on-flex; wafer level package; Anisotropic magnetoresistance; Bonding processes; Conductive adhesives; Electric resistance; Humidity; Nonconductive adhesives; Packaging; Testing; Wafer bonding; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009. IMPACT 2009. 4th International
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-4341-3
  • Electronic_ISBN
    978-1-4244-4342-0
  • Type

    conf

  • DOI
    10.1109/IMPACT.2009.5382308
  • Filename
    5382308