DocumentCode
3132983
Title
Full-speed field-programmable memory BIST architecture
Author
Du, Xiaogang ; Mukherjee, Nilanjan ; Cheng, Wu-Tung ; Reddy, Sudhakar M.
Author_Institution
Mentor Graphics, Wilsonville, OR
fYear
2005
fDate
8-8 Nov. 2005
Lastpage
1173
Abstract
A full-speed field-programmable memory BIST controller is proposed. The proposed instruction and architecture designs enable full-speed operation of not only March algorithms but also some non-linear algorithms that are becoming more and more important in modern memory testing, diagnosis, and failure analysis
Keywords
built-in self test; failure analysis; field programmable gate arrays; memory architecture; failure analysis; field-programmable memory BIST architecture; field-programmable memory BIST controller; full-speed operation; memory diagnosis; memory testing; nonlinear algorithms; Algorithm design and analysis; Built-in self-test; Failure analysis; Fault detection; Hardware; Manufacturing; Medical tests; Memory architecture; System-on-a-chip; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location
Austin, TX
Print_ISBN
0-7803-9038-5
Type
conf
DOI
10.1109/TEST.2005.1584084
Filename
1584084
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