Influence of passivation anneal position on metal coverage dependent mismatch and hot carrier reliability

Author

Chetlur, S. ; Sen, S. ; Harris, E. ; Vaidya, H. ; Kizilyalli, I. ; Gregor, R. ; Harding, B.

Author_Institution

Lucent Technol., AT&T Bell Labs., Orlando, FL, USA

fYear

1999

fDate

1999

Firstpage

21

Lastpage

24

Abstract

Prolonged higher temperature passivation anneals are purported to minimise metal coverage induced transistor mismatch in multi-level-metal (MLM) CMOS circuits. However, process changes that improve unstressed (T=O) device matching do not necessarily lead to better matching under hot carrier stress. As a result, matched transistor parameters can drift disproportionately during circuit operation and increase mismatch. Here, we demonstrate that the popular method of improving mismatch by increasing the post-cap final passivation anneal temperature and time can adversely impact the DC hot carrier ageing (HCA) behaviour. By changing the position of the passivation anneal in the fabrication process flow, the device is made more robust to hot carrier ageing while improving transistor matching

Keywords

CMOS integrated circuits; ageing; annealing; hot carriers; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; integrated circuit reliability; passivation; DC hot carrier ageing; circuit operation; fabrication process flow; high temperature passivation anneals; hot carrier ageing; hot carrier reliability; hot carrier stress; matched transistor parameter drift; metal coverage dependent mismatch; metal coverage induced transistor mismatch; multi-level-metal CMOS circuits; passivation anneal; passivation anneal process position; post-cap final passivation anneal temperature; post-cap final passivation anneal time; process changes; transistor matching; unstressed device matching; Aging; Annealing; CMOS process; Circuits; Hot carriers; Hydrogen; MOSFETs; Passivation; Stress; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 1999. Proceedings of the 1999 7th International Symposium on the

Print_ISBN

0-7803-5187-8

Type

conf

DOI

10.1109/IPFA.1999.791266

Filename

791266