DocumentCode
3133209
Title
A heuristic mapping approach for wormhole switching based Network-on-Chip
Author
Cao, Yafei ; Wang, Dawei ; Li, Sikun
Author_Institution
Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China
fYear
2009
fDate
20-21 Sept. 2009
Firstpage
435
Lastpage
438
Abstract
Network-on-chip mapping and the configuration of the communication parameters are critical process of the NoC design. They significantly influence the performance, area and power of the NoCs. We take the NoC mapping problem and the design of the communication parameters both into account. First, we formalize the problem of NoC mapping. Then we propose an analytical delay model based on wormhole switching. We heuristic map the application model to NoC topology under the constraints of communication delay and obtain the communication parameters automatically. Experiments show that our approach is more comprehensive than previous work and the time consumed by our approach is up to 30% of the reference work.
Keywords
circuit switching; integrated circuit design; logic design; network topology; network-on-chip; NoC design; NoC mapping; NoC topology; analytical delay model; communication delay; communication parameter; heuristic mapping; network-on-chip; wormhole switching; Analytical models; Bandwidth; Communication switching; Delay; Design automation; Discrete event simulation; Energy consumption; Network topology; Network-on-a-chip; Packet switching; Communication Parameters; Network-on-Chip; Wormhole Switching;
fLanguage
English
Publisher
ieee
Conference_Titel
Information, Computing and Telecommunication, 2009. YC-ICT '09. IEEE Youth Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-5074-9
Electronic_ISBN
978-1-4244-5076-3
Type
conf
DOI
10.1109/YCICT.2009.5382322
Filename
5382322
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