DocumentCode
3133219
Title
Is the concern for soft-error overblown?
Author
Galivanche, Rajesh
fYear
2005
fDate
8-10 Nov. 2005
Firstpage
1269
Lastpage
1269
Keywords
Aging; Circuit synthesis; Costs; Coupling circuits; Logic; Nanoscale devices; Process design; Semiconductor device manufacture; Silicon; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Print_ISBN
0-7803-9038-5
Type
conf
DOI
10.1109/TEST.2005.1584101
Filename
1584101
Link To Document