Design tradeoffs for voltage controlled crystal oscillators with built-in calibration mechanisms

Author

Cardoso, J.P. ; Machado da Silva, Jose

Author_Institution

FEUP, Porto, Portugal

fYear

2013

fDate

16-18 Dec. 2013

Firstpage

1

Lastpage

6

Abstract

Timing is a critical issue in communication systems, especially for synchronous communications. These show a high dependence on the clock signal purity due to errors that can be introduced into the decision process. This paper addresses the design, on a 130nm CMOS process, of a Radiation Tolerant Voltage Controlled Quartz Crystal Oscillator (VCXO), including techniques to reduce the influence of radiation and noise on its performance. The VCXO is included on a PLL designed to work within High Energy Physics (HEP) experiments.

Keywords

CMOS analogue integrated circuits; calibration; crystal oscillators; decision theory; integrated circuit design; phase locked loops; voltage-controlled oscillators; CMOS process; HEP; PLL; VCXO; built-in calibration mechanisms; clock signal purity; decision process; design tradeoffs; high energy physics; phase-locked loops; radiation tolerant voltage controlled quartz crystal oscillator; size 130 nm; synchronous communications; Capacitance; Crystals; MOSFET; Phase noise; Tuning; Crystal; High Energy Physics; Large Hadron Collider; Phase-Noise; Radiation Tolerant; Voltage Controlled Quartz Crystal Oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test Symposium (IDT), 2013 8th International

Conference_Location

Marrakesh

Type

conf

DOI

10.1109/IDT.2013.6727100

Filename

6727100