DocumentCode
3133328
Title
ASET: a formal model for system emulation and verification
Author
Bhattacharyya, Swapan ; Bhattacharyya, Joydeep ; Chaudhuri, Adrish Ray
Author_Institution
Jadavpur Univ., Calcutta, India
fYear
2004
fDate
28-30 June 2004
Firstpage
21
Lastpage
28
Abstract
This paper describes a proposed formal model for system specification $ASET (advanced system emulation technique) and discusses the mathematical model underlying the prototyping environment based on ASET. ASET has been developed specifically to aid rapid prototyping of software systems. It provides an environment for system simulation and verification. A tool based on ASET has been developed and can be used to generate executable code directly from design specifications. Active consideration has been given in ASET to concurrent processes and distributed systems. The design specification in ASET implements both distinct control and data flows as well as allowing specification of data dependent control conditions. This paper provides a formal model for the components of ASET and discusses the verification and prediction aspects.
Keywords
data flow analysis; formal specification; formal verification; software prototyping; software tools; ASET; advanced system emulation; data dependent control; data flows; design specification; distributed systems; formal model; prototyping environment; rapid software prototyping; system simulation; system specification; system verification; Design for disassembly; Emulation; Error correction; Mathematical model; Modeling; Predictive models; Prototypes; Software prototyping; Software systems; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Rapid System Prototyping, 2004. Proceedings. 15th IEEE International Workshop on
ISSN
1074-6005
Print_ISBN
0-7695-2159-2
Type
conf
DOI
10.1109/IWRSP.2004.1311090
Filename
1311090
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