DocumentCode :
3133591
Title :
Achieving higher yield through diagnosis
Author :
Tamarapalli, Nagesh
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR
fYear :
2005
fDate :
8-8 Nov. 2005
Lastpage :
1312
Abstract :
With the continuous drive to smaller features, introduction of new manufacturing materials, sub-wavelength lithography, and process and design interaction, achieving acceptable yield at technology nodes 130 nm and below is proving to be a daunting task. At these technology nodes yield is limited not just by random defects but also increasingly by systematic yield detracting mechanisms. In addition, a larger portion of the defects are becoming non-visual and/or parametric in nature. In fact many defects that cause electrical failures are not detectable by the traditional defect sourcing techniques such as inline inspection
Keywords :
application specific integrated circuits; design for testability; fault diagnosis; integrated circuit testing; integrated circuit yield; 130 nm; electrical failures; inline inspection; integrated circuit testing; random defects; sub-wavelength lithography; Application specific integrated circuits; Built-in self-test; Costs; Electronic design automation and methodology; Foundries; Large scale integration; Logic design; Logic devices; Logic testing; Production;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
Type :
conf
DOI :
10.1109/TEST.2005.1584128
Filename :
1584128
Link To Document :
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