Title :
Economics and design challenges in implementing CMOS Transimpedance Amplifers for 10Gb/s operation
Author_Institution :
Basas Microelectron., Beijiing, China
Abstract :
This paper examines the technological challenges in implementing 10 Gb/s Transimpedance Amplifiers in standard CMOS process technology. Circuit techniques for enabling 10 Gb/s CMOS circuit operation are discussed. Paper concludes with measurements results for an actual 10 Gb/s CMOS Transimpedance Amplifier.
Keywords :
CMOS analogue integrated circuits; amplifiers; CMOS; bit rate 10 Gbit/s; circuit techniques; transimpedance amplifers; CMOS process; CMOS technology; Circuits; Cost function; Fuel economy; Heterojunction bipolar transistors; Indium phosphide; Optical amplifiers; Power generation economics; Universal Serial Bus;
Conference_Titel :
OptoElectronics and Communications Conference, 2009. OECC 2009. 14th
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-4102-0
Electronic_ISBN :
978-1-4244-4103-7
DOI :
10.1109/OECC.2009.5221591
