Title :
NOC synthesis vs ITRS predictions: The challenges of linear programming based synthesis
Author_Institution :
ENSTA ParisTech, Palaiseau, France
Abstract :
Network on chip are fundamental in the performance of complex system on chip. Numerous solutions have been proposed both for regular and irregular topologies. Irregular or custom topologies present numerous benefits with regard to area/performance optimizations and can be automatically generated through NOC synthesis flows. NOC synthesis generates NOC topologies from application requirements coregraphs. NOC synthesis techniques use either exact or heuristic techniques. So far NOC synthesis techniques have not been benchmarked against ITRS roadmaps. We propose in this paper to benchmark linear programming based NOC synthesis techniques using NOCBENCH v.1.0 benchmarks. The results show that new models and techniques are needed to overcome complexity of future manycore.
Keywords :
integrated circuit design; linear programming; network topology; network-on-chip; ITRS prediction; NOC synthesis flows; NOC topology; NOCBENCH v.1.0 benchmarks; application requirement coregraphs; area-performance optimization; complex system-on-chip; custom topology; heuristic technique; irregular topology; linear programming-based synthesis; network-on-chip; regular topology; Decision support systems; Hafnium;
Conference_Titel :
Design and Test Symposium (IDT), 2013 8th International
Conference_Location :
Marrakesh
DOI :
10.1109/IDT.2013.6727135