Low noise optimization of InP HEMTs

The influence of the noise figure on both gate and drain source voltage, threshold voltage and transistor size have been investigated for the design of low noise integrated circuits. Therefore, a device model for both high frequency small signal and noise behavior of InP-HEMTs, depending on both gate and drain voltage, has been developed. It was found that the lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V_ds=0.6 V. However, it was shown for the first time that the bias for lowest noise is frequency dependent. Modeling scaling effects of the noise behavior shows, that lowest noise is observed for a gate width of 1×40 μm. Multi-finger layouts are preferable for gate widths above 70 μm. Furthermore, it is shown that the optimum width of each finger decreases with the number of fingers