RSD based Karatsuba multiplier for ECC processors

This paper proposes a 256 Redundant Signed Digits hardware multiplier based on Karatsuba that is suitable for prime field ECC processors. Redundant representation is essential for prime field ECC processors as the basis for carry free arithmetic. The proposed multiplier works by applying Karatsuba method at two levels where three recursively constructed blocks are used to perform large integer multiplication iteratively. Different design alternatives are presented and implemented in Xilinx Virtex-5 FPGA. A pipelined multiplier with a recursive blocks of size 64 digits can perform one full 256 RSD digits multiplication within 1.08μs, operating at maximum frequency of 61.91 MHz.