Analysis of surface-state effects on gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

Gate-lag or slow current transient behaviour in GaAs MESFETs is studied by two-dimensional analysis including surface-state effects. It is shown that in a recessed-gate structure, the gate-lag is reduced to some extent by increasing the recess depth, but it may not be suppressed as much as expected because surface states around the gate affect the turn-on characteristics. However, by introducing the buried-gate structure where the gate electrode is attached to the vertical planes of the recess and also to the same planes as the drain electrode, the surface-state effects are minimized, and the gate-lag can be greatly reduced