Title :
A comparative study of charge trapping effects in LDD surface-channel and buried-channel pMOS transistors using charge profiling and threshold voltage shift measurements
Author :
Kok, C.K. ; Chew, W.C. ; Chim, W.K. ; Chan, D.S.H. ; Leang, S.E.
Author_Institution :
Centre for Integrated Circuit Failure Analysis & Reliability, Nat. Univ. of Singapore, Singapore
Abstract :
Extracted charge profiles of lightly-doped drain (LDD) surface-channel and buried-channel pMOS devices stressed under hot-carrier injection conditions reveal predominant electron trapping near the gate edge at the drain region in both cases. From threshold voltage measurements, there is some evidence of hole trapping after long stress times in surface-channel pMOSFETs, but not in buried-channel devices
Keywords :
MOSFET; buried layers; doping profiles; electron traps; hole traps; hot carriers; semiconductor device testing; voltage measurement; LDD buried-channel pMOS transistors; LDD surface-channel pMOS transistors; buried-channel pMOSFETs; charge profiles; charge profiling; charge trapping effects; drain region; electron trapping; gate edge; hole trapping; hot-carrier injection stress; lightly-doped drain buried-channel pMOS devices; lightly-doped drain surface-channel pMOS devices; stress times; surface-channel pMOSFETs; threshold voltage measurements; threshold voltage shift measurements; Charge measurement; Current measurement; Degradation; Electron traps; Hot carriers; MOS devices; MOSFETs; Stress measurement; Threshold voltage; Voltage measurement;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 1999. Proceedings of the 1999 7th International Symposium on the
Print_ISBN :
0-7803-5187-8
DOI :
10.1109/IPFA.1999.791334
