A 0.15 /spl mu/m DRAM technology node for 4 Gb DRAM

Author

Kim, K.N. ; Jeong, H.S. ; Jeong, G.T. ; Cho, C.H. ; Yang, W.S. ; Sim, J.H. ; Lee, K.H. ; Koh, G.H. ; Ha, D.W. ; Bae, J.S. ; Lee, J.-G. ; Park, B.J. ; Lee, J.G.

Author_Institution

Technol. Dev., Samsung Electron. Co., Yongin-City, South Korea

fYear

1998

fDate

9-11 June 1998

Firstpage

16

Lastpage

17

Abstract

The DRAM process technology has been on the leading edge of semiconductor technology, and the density of DRAM has been quadrupled every three years. 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) was successfully manufactured and much attention is now given to the process technology for 4 Gb DRAM based on 0.15 /spl mu/m technology node or smaller than 0.15 /spl mu/m technology node. 0.15 /spl mu/m technology node is considered to be transition node between 0.18 /spl mu/m which KrF lithography is used on 200 mm wafers and 0.13 /spl mu/m node in which ArF lithography will be used on 300 mm wafers. In this paper, key process and integration technologies for 0.15 /spl mu/m DRAM technology node are developed in order to satisfy both 0.18 /spl mu/m technology node and 0.13 /spl mu/m node. The process and integration technologies employed in 0.15 /spl mu/m technology node are verified with an experimental 16 Mb DRAM.

Keywords

DRAM chips; integrated circuit technology; photolithography; 0.15 micron; 4 Gbit; ArF lithography; DRAM technology node; KrF lithography; integration technology; process technology; semiconductor technology; CMOS logic circuits; CMOS technology; Filling; Lead compounds; Lithography; Manufacturing processes; Oxidation; Printing; Proximity effect; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4770-6

Type

conf

DOI

10.1109/VLSIT.1998.689181

Filename

689181