A 0.15 /spl mu/m DRAM technology node for 4 Gb DRAM

The DRAM process technology has been on the leading edge of semiconductor technology, and the density of DRAM has been quadrupled every three years. 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) was successfully manufactured and much attention is now given to the process technology for 4 Gb DRAM based on 0.15 /spl mu/m technology node or smaller than 0.15 /spl mu/m technology node. 0.15 /spl mu/m technology node is considered to be transition node between 0.18 /spl mu/m which KrF lithography is used on 200 mm wafers and 0.13 /spl mu/m node in which ArF lithography will be used on 300 mm wafers. In this paper, key process and integration technologies for 0.15 /spl mu/m DRAM technology node are developed in order to satisfy both 0.18 /spl mu/m technology node and 0.13 /spl mu/m node. The process and integration technologies employed in 0.15 /spl mu/m technology node are verified with an experimental 16 Mb DRAM.