Study of the Power Factor Correctors with fast output-voltage feedback loop

When a power factor corrector (PFC) is designed with a fast output-voltage feedback loop, the study of the power stage changes in comparison with the one carried out with a slow output-voltage feedback loop. This is a consequence of the voltage ripple that appears in the control signal. A study of the static behaviour of a PFC with fast output-voltage feedback loop is carried out in this paper by using two parameters: the module of the relative voltage ripple of the control signal and its phase angle. These parameters do not change with the load and they determine the line total harmonic distortion (THD) and the power factor (PF) at the input of the PFC. Moreover, these parameters also determine the maximum power handled by the converter according to the EN 61000-3-2 regulations in class A and in class B. On the other hand, when the converter must comply with the EN 61000-3-2 regulations in class C or in class D, the compliance does not depend on the power handled by the PFC and not all the possible combinations of the relative voltage ripple of the control signal and its phase angle achieve compliance with the above mentioned regulations. Finally, the study has been experimentally verified.