FPGA implementation of V-BLAST detection algorithm in MIMO system

This paper presents FPGA implementation of various V-BLAST detection algorithms which are maximum likelihood, zero forcing and minimum mean squared error. Firstly, the MIMO V-BLAST system structure, the mathematical models and a variety of receiver detection algorithms have been studied detailedly. And then we analyze the characteristic and performance of typical algorithms and focus on using the Verilog hardware description language to implement the V-BLAST system architecture and the three detection algorithms on the Xilinx´s Vertex Series FPGA, which can give good performance. Ultimately, these simulation results had been compared with each other in terms of complexity and error performance.